mojo_top Project Status (05/21/2013 - 09:28:16) | |||
Project File: | Mojo-Clock.xise | Parser Errors: | No Errors |
Module Name: | mojo_top | Implementation State: | Programming File Generated |
Target Device: | xc6slx9-2tqg144 |
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No Errors |
Product Version: | ISE 14.4 |
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156 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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All Constraints Met |
Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [+] |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [+] |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Mon Feb 11 13:13:32 2013 | |
WebTalk Report | Current | Tue May 21 09:28:15 2013 | |
WebTalk Log File | Current | Tue May 21 09:28:16 2013 |